Optical integrated circuits (OICs) may be sensitive to electrostatic discharge (ESD) events. In many applications, back end-of-line (BEOL) metallization may be formed on top of the optical layer of a photonic chip. The BEOL layers may be used for routing electrical signals as well as to form a seal ring around the photonic chip. The seal ring may be formed around the perimeter of OICs to provide protection from potentially harmful ESD events. For example, the seal ring may be electrically coupled to an ESD diode which may provide a pathway to a ground connection in the presence of high voltage and/or current conditions. However, seal rings formed exclusively from metal layers may not provide complete protection from potentially harmful ESD events when the photonic chip includes external optical connections.
For example, in applications where a cavity in the BEOL layers is utilized to facilitate optical coupling between an OIC and an interposer, the optical coupling may be achieved using adiabatic or evanescent coupling between OIC waveguides and interposer waveguides. In this case, adiabatic coupling between the waveguides may require openings to be formed in the metal layers of a BEOL seal ring. Depending on the waveguide and cladding materials, these openings may allow electrical charge to pass through the seal ring during an ESD event. Therefore, a seal ring that is compatible with external optical connections while maintaining a high level of electrical isolation may be desirable.